This invention relates to integrated circuits and more particularly to monolithic integrated circuits having circuit components formed on a common substrate and which are electrically isolated from each other throughout the substrate.
As used herein, the expression "monolithic integrated circuit" refers to a single substrate or wafer of semiconductive material which may, typically, be monocrystalline. Individual active or passive components are formed on the surface of the wafer and, when appropriately interconnected, results in the desired circuit network. Accordingly, such circuit networks require electrical isolation between the various circuit components formed on the wafer.
As discussed in my co-pending patent application Ser. No. 618,717, filed on or about Oct. 1, 1975, entitled "Dielectrically Isolated Semiconductor Device" and assigned to the assignee of the subject application, I disclose a method wherein a semiconductor wafer of one conductivity is processed to have an epitaxial layer of semiconductive material of an opposite conductivity on the surface of the wafer. A nitride layer is then formed over the epitaxial layer. The processing includes etching a first set of parallel grooves through the nitride layer and partially through the epitaxial layer, after which, a second set of parallel grooves are etched through the nitride layer across the first set of grooves. The grooved wafer is then subjected to an oxidation step to convert the exposed grooved portions to an insulating oxide. The resulting structure is one having a first set of grooves that extend completely through the epitaxial layer to the wafer and a second set of crossing grooves that extend only partially through the epitaxial layer. Since the grooves are filled with an insulator material, discrete "islands" are thus formed which are electrically isolated one from another.
After the dielectrically isolated islands have been formed, by any method of manufacture, active or passive circuits are formed in or on the exposed surface of the islands and interconnecting leads are then formed on the surface of the device for connection to the various elements of the individual circuits. However, in the prior art manufacture of these integrated circuits, it has been found that a significant portion of the total area of the wafer is occupied by the isolation regions between adjacent islands. Since large areas of isolation reduce the number of active devices in a given, fixed area, the resultant chip will have an undesirably lower packing density.
In instances where isolation between semiconductor devices, either of the bipolar transistor type or MOS, is required, the isolation of islands by regions of dielectric insulation is highly desirable. The foregoing technique represents an improvement in both my co-pending application as well as the prior art in that, by using a combination of ion implantation and diffusion, I am able to accommodate complimentary (C-MOS) devices which require the aforementioned isolation. In addition, by using the foregoing technique, I am also able to accommodate various other types of active devies, such as, for example, diodes. Additionally, my novel process can provide a higher packing density of the final monolithic integrated circuit than heretofore possible, since less area is required for the isolation regions.